Back-gated OFET Interdigitated Substrate FIPMS148-1PAK

Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)
Layer structure:

• Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3)
• Gate oxide: 230 nm ± 10 nm SiO2 (thermal oxidation)
• Drain/source: 30 nm Au with 10 nm high work function adhesion layer (ITO), by lift-off technique
• Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone)
• Layout: see images
• Test chip size: 15 x 15 mm2
• No. of chips: 60 per wafer
• Contact pads: 0.5 x 0.5 mm2
• No. of transistors: 16 per wafer

4 x transistors L= 2.5 µm W= 10 mm
4 x transistors L= 5 µm W= 10 mm
4 x transistors L= 10 µm W= 10 mm
4 x transistors L= 20 µm W= 10 mm
Back-gated OFET Interdigitated Substrate (organic field-effect transistor) can be used in the fabrication of chemical sensors for potential usage in pH sensing and detection of immunoassays. It can also be used in the fabrication of biosensors by coating the sheets of the FET with a specific antibody for the detection of SARS-CoV-2. FET based biosensors can be potentially used in clinical diagnosis, point of care testing, and on-site detection.
diced wafer on foil with air tight packaging
Recommendation for resist removal:
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).
Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.
Store the wafers at a cool and dark place and protect them against sun.
Resist layer was applied to prevent damage from scratches.
Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.
Product of Fraunhofer IPMS

form	chips (diced), chips (each 15 x 15 mm2)
packaging	pack of 1 (wafer of 60 diced chips)
storage temp.	15-25°C